Job Description

Job Responsibilities:

• Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
• Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
• Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
• Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
• Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.

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Preferred Qualifications:

• 7+ years of experience in physical design roles and related activities.
• Proven ability to adhere to tight schedules and implement low-power design techniques.
• Experience in System-on-Chip (SoC) design and implementation.
• Expertise in sub-7nm node technologies.
• Familiarity with industry-standard EDA tools and their capabilities.
• Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.

Annual Hiring Range/Hourly Rate:

$87,400.00 - $165,000.00

Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer.

Location:

US-CA-San Jose, California (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services

EEO Statement:

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)

All Arrow job postings are for existing job vacancies . We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Job Tags

Hourly pay, Full time, Work experience placement

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